Some types of LSI (Large Scale Integrated circuit) have an analog circuit such as a PLL (Phase Locked Loop) circuit mounted thereon. The PLL circuit, having a function of multiplying the clock frequency or performing skew adjustment of the clock inside the LSI, is applied as a circuit for increasing the speed and scale of the LSI.
Additionally, in recent years, there is proposed, in addition to the PLL circuit which integrally multiplies the frequency, a PLL circuit including a frequency dividing circuit with a variable frequency dividing ratio such as an SSCG (Spread Spectrum Clock Generator), or a Fractional-N PLL having a decimal multiplication function.
When an LSI is designed, a simulation model describing the PLL circuit in terms of functionality using a hardware description language such as Verilog is created, and a logic simulation is performed in order to verify the operation of the PLL circuit.
The simulation model of the PLL circuit which integrally multiplies the frequency includes a phase difference detection unit configured to detect a phase difference between a reference clock and a feedback clock, and a lock detection unit configured to determine, from the phase difference, whether or not the output clock has reached a target frequency. In addition, there are also included a frequency adjustment unit configured to adjust the frequency based on the phase difference, a clock output unit configured to output the clock of the adjusted frequency, and a frequency dividing unit configured to divide the frequency of the output clock and generate a feedback clock.
See, for example, International Publication Pamphlet No. WO 2008/117361.
In a PLL circuit such as an SSCG in which the frequency dividing ratio varies, the frequency dividing ratio is always varying and therefore a phase difference occurs between the reference clock and the feedback clock even when the frequency of the output clock approaches the target frequency. With the logic simulation using the simulation model as described above, the next frequency of the output clock is immediately determined based on the phase difference between the reference clock and the feedback clock. Therefore, a frequency variation which is more rapid than that in the actual PLL circuit is likely to occur, whereby it has been difficult to reproduce the circuit operation with high precision.